As the microelectronics industry progresses further in the deep submicron technology, one of the major issues facing the chip design industry is the occurrence of on-chip interconnect crosstalk faults. A crosstalk fault occurs when two neighboring signal lines affect each other due to the coupling capacitance and inductance between them, which results in the propagation of wrong logic values to the gates or registers driven by these signal lines. Typically, crosstalk prone fault sites are detected by auditing the chip layout, and corrective measures are taken in the layout to avoid the possibility of a crosstalk fault occurring by separating these signal lines further apart.